Generation of Scheduling Functions Supporting LSGP-Partitioning

In this paper, we present an approach to determine scheduling functions suitable for the design of processor arrays. The considered scheduling functions support a followed LSGP-partitioning of the processor array by allowing to execute the tasks of processors of the full-size array mapped into one processor of the partitioned processor array in an arbitrary order. Several constraints are derived to ensure the causality of computations and to prevent access conflicts to both modules and registers. We propose an optimization problem generating the scheduling functions and outline its implementation as an integer linear program. The proposed methods are also applicable for the mapping of algorithms to parallel architectures. In this case, the scheduling function produces identical, independent small threads which can be combined to utilize the target architecture as much as possible. 1. Introdu tion This paper contributes to the design of processor arrays for regular algorithms. We derive an optimization problem for generating a scheduling function leading to the minimum latency of the processor array. Thereby both a limited number of modules implementing operations in the processors and a limited number of available registers in the processors can be incorporated. The main feature of our approach is the support of a partitioning of the resulting processor array by keeping various degrees of freedom to define the partitions. Thereby, we assume that the sequence of operations in each processor of the full-size array is divided into tasks of a length equal to one iteration interval. Then, we derive constraints allowing to evaluate the parallel tasks of processors of the full-size array in one processor of the partitioned processor array in an arbitrary order without causality conflicts. In the course of the paper, we consider two scheduling functions. The first scheduling function, called uniform affine scheduling function, is well-studied in approaches concerning resource constraint scheduling. The second function we have called quasi uniform scheduling function since a floor operator is used to ensure besides a periodic schedule in each processor, that each processor performs at each time the same operation. This allows to exchange operations between processors in an arbitrary manner. An additional constraint ensures for both scheduling functions that entire iterations can be exchanged between processors, and that parallel iterations can be evaluated sequentially in one processor. Thus, a straightforward partitioning of the processor array is possible. Furthermore, the approach can be used to ensure an optimal utilization of a multiprocessor system by consideration of each iteration as a thread which can be arbitrarily distributed among the available processors. The research was supported by the ”Deutsche Forschungsgemeinschaft”, in the project A1/SFB358.